1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which communicates data with the outside in synchronization with a rise and fall of an external clock, and carries out a processing for access to a memory cell for a plurality of cycles with an operation at a higher frequency.
2. Description of the Background Art
With a demand for an operation with a higher frequency in the semiconductor memory device, a double data rate SDRAM (hereinafter, referred to as a DDR SDRAM) communicating data with the outside in synchronization with rising and falling edges of an external clock has been developed and put into practical use.
A first-generation DDR SDRAM referred to as a DDR-I performs a 2-bit prefetch operation, in which 2-bit data received in synchronization with the successive rising and falling edges of the external clock is written at a time into a memory cell array for each cycle, in each of a plurality of data input circuits (with regard to data read, the 2-bit data is read at a time from the memory cell array for each cycle, corresponding to each of a plurality of data output circuits, and then, the 2-bit data is sequenced and output to the outside every half cycle).
Recently, as a DDR SDRAM attaining an operation at a further higher frequency, a second-generation DDR SDRAM referred to as a DDR-II has attracted attention. The DDR-II is standardized by “JEDEC” (Joint Electron Device Engineering Council), which is an organization standardizing electronic devices in the United States.
The DDR-II is first characterized by a 4-bit prefetch operation. In the DDR-II, a time period itself from when execution of an internal processing is instructed until when memory cell is accessed is not different from that in the DDR-I. Therefore, the processing for access to the memory cell is not completed within one cycle, because an operation frequency (an external clock frequency) is higher in the DDR-II. Accordingly, in the DDR-II, two cycles serve as one operation unit for the internal processing, and the memory cell is accessed for each operation unit.
A write operation will be described as an example. In each of the data input circuits, data of four bits received in synchronization with the rising and falling edges of the external clock during consecutive two cycles is written at a time into the memory cell array every two cycles. In this manner, in the DDR-II, a data transfer rate within the device is doubled, compared to the DDR-I performing the 2-bit prefetch operation, and thus, the operation frequency is enhanced.
Secondly, the DDR-II is characterized by using an additive latency (hereinafter, also referred to as “AL”), a read latency (hereinafter, also referred to as “RL”), and a write latency (hereinafter, also referred to as “WL”) as a technique to improve operation efficiency of a system having the semiconductor memory device mounted. In the DRAM including the DDR SDRAM, a time period from when an activation command (ACT command) is received until when a read command or a write command (hereinafter, also collectively referred to as “column command”) is received is defined by a delay time tRCD as an operation specification. When viewed from the system, however, from the viewpoint of the operation efficiency, it is desirable to be able to immediately issue the column command in a following cycle after the issue of the ACT command. Therefore, in the DDR-II, the column command will be acceptable in a cycle following the reception of the ACT command, and the column command is delayed by the number of cycles defined with AL within the device, to secure time tRCD.
In addition, RL represents the number of cycles defined with (AL+CL), and represents the number of cycles from when the DDR-II receives the read command from the outside until when the DDR-II starts to output data to the outside. WL represents the number of cycles defined with (RL−1), and represents the number of cycles from when the DDR-II receives the write command from the outside until when the data write operation is started.
In doing so, from a viewpoint of the system having the DDR-II mounted, the column command can successively be issued after the ACT command, without taking into account delay time tRCD. That is, an efficient program can be set up.
As described above, in the DDR-II, two cycles of the external clock serve as one operation unit. Therefore, the system utilizing the DDR-II is defined so as to issue a column command at an interval of at least two cycles, during which an issue of a precharge command (PRE command) is prohibited.
On the other hand, a command decoder used in a conventional DRAM including the DDR-I generates an internal control command corresponding to a control command received from the outside as it is, in response to the control command. Therefore, when the control command is input every cycle, the command decoder generates the internal control command every cycle.
In such a case, when the conventional command decoder is used in the DDR-II, and if the DDR-II receives an improper column command issued in subsequent cycle, for example, the processing for access to the memory cell will overlap within one operation unit, and the data in the memory cell will be destroyed.
In addition, the internal control commands corresponding to a plurality of control commands the system issued at different timings may simultaneously be generated within the DDR-II with AL and WL. For example, in the DDR-II, the internal control command corresponding to the read command is generated after the number of cycles defined by AL, after the read command is received. Meanwhile, the internal control command corresponding to the write command is generated after the number of cycles defined by WL, after the write command is received. Therefore, when the DDR-II receives the read command after the write command, both internal control commands may be generated simultaneously. Further, the internal control command corresponding to the read command received later may be generated before the internal control command corresponding to the preceding write command is generated.
In such a case as well, as in the example in which the column commands are input in consecutive cycles, the processing for access to the memory cell may overlap within one operation unit, and the data in the memory cell may be destroyed.